M16C26A Datasheet, PDF (50/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5. Reset
Voltage down detection interrupt generation circuit
DF1, DF0
00b
01b
Voltage Down Detection Circuit
10b
VC27
D4INT clock(the
11b
clock with which it ^1/8
1/2
1/2
1/2
operates also in
wait mode)
The D42 bit is set to “0” (not detected)
by program. the VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
VC13
D42
VCC
VREF
+
Noise
-
Rejection
(Rejection Range:200 ns)
Voltage down
detection signal
Noise Rejection
Circuit
Digital
Filter
The Voltage down detection
signal becomes “H” when the
VC27 bit is set to “0” (disabled)
CM10
D41
Watchdog Timer Block
CM02
WAIT instruction(wait mode)
Watchdog timer
underflow signal
D43
This bit is set to “0”(not detected) by program.
D40
Watchdog
timer interrupt
signal
Voltage down
detection
interrupt signal
Oscillation stop,
re-oscillation
detection
interrupt signal
Non-maskable
interrupt signal
Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block
VCC
VC13 bit in VCR1 register
sampling
sampling
sampling
sampling
Output of the digital filter ⁽²⁾
D42 bit in D4INT register
No voltage down detection interrupt signals are
generated when the D42 bit is “1”.
Set to “0” by program (not detected)
Voltage down detection
interrupt signal
NOTES :
1. D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled).
2. Output of the digital filter is shown in Figure 5.5.1.1.
Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example
Rev. 2.00 Feb.15, 2007 page 33 of 329
REJ09B0202-0200