M16C26A Datasheet, PDF (182/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Table 13.1.3.2.1. STSPSEL Bit Functions
Function
STSPSEL = 0
STSPSEL = 1
Output of SCL2 and SDA2 pins Output transfer clock and data/ The STAREQ, RSTAREQ and
Program with a port determines STPREQ bit determine how the
how the start condition or stop start condition or stop condition is
condition is output
output
Start/stop condition interrupt
Start/stop condition are de-
Start/stop condition generation are
request generation timing
tected
completed
(1) In slave mode,
CKDIR is set to "1" (external clock)
STPSEL bit 0
SCL2
1st
2nd
3rd 4th
5th 6th 7th
8th
9th bit
SDA2
Start condition detection
interrupt
Stop condition detection
interrupt
(2) In master mode,
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
STPSEL bit
SCL2
SDA2
Set to "1" by
a program
Set to "0" by
a program
1st
2nd
3rd 4th
Set to "1" by Set to "0" by
a program
a program
5th
6th
7th
8th
9th bit
Set STAREQ to "1" (start)
Start condition detection
interrupt
Figure 13.1.3.2.1. STSPSEL Bit Functions
Set STPREQ
to "1" (start)
Stop condition detection
interrupt
13.1.3.3 Arbitration
Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising
edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the
same time unmatching is detected during check, and is cleared to “0” when not detected. In cases
when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to
“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
Rev. 2.00 Feb.15, 2007 page 165 of 329
REJ09B0202-0200