M16C26A Datasheet, PDF (73/352 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7. Clock Generation Circuit
Table 7.6.1. Allowed Transition and Setting
High-speed mode,
middle-speed mode
Low-speed mode2
High-speed mode, _{Low-speed mode2} Low power
middle-speed mode
dissipation mode
8
(9)⁷
--
(8)
(11)^{1, 6}
State after transition
PLL operation
mode2
On-chip oscillator
mode
(13)³
(15)
On-chip oscillator
low power
dissipation mode
--
--
(8)
--
Low power dissipation
mode
--
(10)
--
PLL operation mode2
(12)³
--
--
--
--
--
--
On-chip oscillator mode
(14)⁴
(9)⁷
--
--
On-chip oscillator
low power dissipation
--
--
--
--
mode
Stop mode
(18)⁵
(18)
(18)
--
8
(10)
(18)⁵
(11)¹
8
(18)⁵
Wait mode
(18)
(18)
(18)
--
(18)
(18)
NOTES:
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as a clock for the timers A and B.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to 1 (division by 8 mode).
6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1 (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
No
division
No division
Divided by 2 (3)
Divided by 4 (3)
Divided by 8 (3)
Divided by 16 (3)
No division (2)
Divided by 2
--
Divided by 4
--
Divided by 8
--
Divided by 16 --
Sub clock oscillating
Divided Divided Divided
by 2 by 4 by 8
(4)
(5)
(7)
(5)
(7)
(4)
(7)
(4)
(5)
(4)
(5)
(7)
--
--
--
(2)
--
--
--
(2)
--
--
--
(2)
--
--
--
9. ( ) : setting method. Refer to following table.
Divided
by 16
(6)
(6)
(6)
(6)
--
--
--
--
(2)
No
division
(1)
--
--
--
--
(3)
(3)
(3)
(3)
Sub clock turned off
Divided Divided Divided Divided
by 2
by 4
by 8 by 16
--
--
--
--
(1)
--
--
--
--
(1)
--
--
--
--
(1) --
--
--
-- (1)
(4) (5)
(7) (6)
(5)
(7) (6)
(4)
(7) (6)
(4) (5)
(6)
(4) (5)
(7)
--: Cannot transit
Stop mode
(16)¹
(16)¹
(16)¹
Wait mode
(17)
(17)
(17)
--
--
(16)¹
(17)
(16)¹
(17)
--
--
--: Cannot transit
Setting
Operation
(1)
CM04 = 0
Sub clock turned off
(2)
CM04 = 1
Sub clock oscillating
(3)
CM06 = 0,
CM17 = 0 , CM16 = 0
CPU clock no division mode
(4)
CM06 = 0,
CM17 = 0 , CM16 = 1
CPU clock division by 2 mode
(5)
CM06 = 0,
CM17 = 1 , CM16 = 0
CPU clock division by 4 mode
(6)
CM06 = 0,
CM17 = 1 , CM16 = 1
CPU clock division by 16 mode
(7)
CM06 = 1
CPU clock division by 8 mode
(8)
CM07 = 0
Main clock, PLL clock,
or on-chip oscillator clock selected
(9)
CM07 = 1
Sub clock selected
(10)
CM05 = 0
Main clock oscillating
(11)
(12)
(13)
(14)
CM05 = 1
PLC07 = 0,
CM11 = 0
PLC07 = 1,
CM11 = 1
CM21 = 0
Main clock turned off
Main clock selected
PLL clock selected
Main clock or PLL clock selected
(15)
CM21 = 1
On-chip oscillator clock selected
(16)
CM10 = 1
Transition to stop mode
(17)
wait instruction
Transition to wait mode
(18) Hardware interrupt Exit stop mode or wait mode
CM04, CM05, CM06, CM07 : Bits in the CM0 register
CM10, CM11, CM16, CM17 : Bits in the CM1 register
CM20, CM21
: Bits in the CM2 register
PLC07
: Bit in the PLC0 register
Rev. 2.00 Feb.15, 2007 ^{page 56} of 329
REJ09B0202-0200