MC68HC08AS32A Datasheet, PDF (90/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
Table 4-4. BDLC Transmit In-Frame Response
Control Bit Priority Encoding
Write/Read
TSIFR
0
1
0
0
Write/Read
TMIFR1
0
X
1
0
Write/Read
TMIFR0
0
X
X
1
Actual
TSIFR
0
1
0
0
Actual
TMIFR1
0
0
1
0
Actual
TMIFR0
0
0
0
1
The BDLC supports the in-frame response (IFR) feature of J1850 by setting
these bits correctly. The four types of J1850 IFR are shown below. The purpose
of the in-frame response modes is to allow multiple nodes to acknowledge
receipt of the data by responding with their personal ID or physical address in a
concatenated manner after they have seen the EOD symbol. If transmission
arbitration is lost by a node while sending its response, it continues to transmit
its ID/address until observing its unique byte in the response stream. For VPW
modulation, because the first bit of the IFR is always passive, a normalization
bit (active) must be generated by the responder and sent prior to its ID/address
byte. When there are multiple responders on the J1850 bus, only one
normalization bit is sent which assists all other transmitting nodes to sync up
their response.
HEADER
DATA FIELD
CRC
TYPE 0 — NO IFR
HEADER
DATA FIELD
CRC
NB ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
HEADER
DATA FIELD
CRC
NB ID1
ID N
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
HEADER
DATA FIELD
CRC
NB
IFR DATA FIELD
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier (usually the physical address of the responder(s))
Figure 4-20. Types of In-Frame Response (IFR)
CRC
(OPTIONAL)
Data Sheet
90
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
MC68HC08AS32A — Rev. 1
MOTOROLA