MC68HC08AS32A Datasheet, PDF (87/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
f_XCLK Frequency
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
Table 4-3. BDLC Rate Selection
R1
R0
Division
0
0
1
0
1
2
1
0
4
1
1
8
0
0
1
0
1
2
1
0
4
1
1
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in
run mode. It does not affect CPU interrupt requests when exiting the BDLC stop
or BDLC wait modes. Interrupt requests will be maintained until all of the
interrupt request sources are cleared by performing the specified actions upon
the BDLC’s registers. Interrupts that were pending at the time that this bit is
cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the BDLC, the
BDLC state vector register (BSVR) can be polled periodically by the
programmer to determine BDLC states. See 4.6.4 BDLC State Vector
Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See
4.7.2 Stop Mode and 4.7.1 Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
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Data Sheet
87