MC68HC08AS32A Datasheet, PDF (257/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
I/O Registers
NOTE:
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIM counter registers matches the
value in the TIM channel x registers.
When CHxIE = 1, clear CHxF by reading TIM channel x status and control
register with CHxF set, and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing logic 0 to
CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB
exists only in the TIM channel 0, TIM channel 2, and TIM channel 4 status and
control registers.
Setting MS0B disables the channel 1 status and control register and reverts
TCH1 pin to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts
TCH3 pin to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts
TCH5 pin to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB–ELSxA ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. (See Table 16-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB–ELSxA = 00, this read/write bit selects the initial output level of
the TCHx pin once PWM, input capture, or output compare operation is
enabled. (See Table 16-2.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
Before changing a channel function by writing to the MSxB or MSxA bit, set the
TSTOP and TRST bits in the TIM status and control register (TSC).
MC68HC08AS32A — Rev. 1
MOTOROLA
Timer Interface (TIM)
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Data Sheet
257