MC68HC08AS32A Datasheet, PDF (111/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Interrupts
5.6 Interrupts
NOTE:
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL
can generate a CPU interrupt request every time the LOCK bit changes state. The
PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL.
PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled
or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the
request was due to an entry into lock or an exit from lock. When the PLL enters
lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT
source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the
application is not frequency sensitive, interrupts should be disabled to prevent PLL
interrupt service routines from impeding software performance or from exceeding
stack limitations.
Software can select the CGMVCLK divided by two as the CGMOUT source even
if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL
is locked before setting the BCS bit.
5.7 Special Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
5.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and PLLON bits
in the PLL control register (PCTL). Less power-sensitive applications can
disengage the PLL without turning it off. Applications that require the PLL to wake
the MCU from wait mode also can deselect the PLL output without turning off the
PLL.
5.7.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN signal low,
disabling the CGM and holding low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock (CGMVCLK) divided by two
driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control
register (PCTL), thereby selecting the crystal clock (CGMXCLK) divided by two as
the source of CGMOUT. When the MCU recovers from STOP, the crystal clock
divided by two drives CGMOUT and BCS remains clear.
MC68HC08AS32A — Rev. 1
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
111