MC68HC08AS32A Datasheet, PDF (228/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
15.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests, as
shown in Table 15-3.
Table 15-3. SPI Interrupts
Flag
SPTE (transmitter empty)
SPRF (receiver full)
OVRF (overflow)
MODF (mode fault)
Request
SPI transmitter CPU interrupt request (SPTIE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1, MODFEN = 1)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate
transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate
receiver CPU interrupt, provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to
generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set
so that only the OVRF flag is enabled to generate receiver/error CPU interrupt
requests.
Two sources in the SPI status and control register can generate CPU interrupt
requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte
transfers from the shift register to the receive data register. If the SPI
receiver interrupt enable bit, SPRIE, is also set, SPRF can generate an SPI
receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a
byte transfers from the transmit data register to the shift register. If the SPI
transmit interrupt enable bit, SPTIE, is also set, SPTE can generate an
SPTE CPU interrupt request.
15.8 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and
transmitted. For an SPI configured as a master, a queued data byte is transmitted
immediately after the previous transmission has completed. The SPI transmitter
empty flag (SPTE in SPSCR) indicates when the transmit data buffer is ready to
accept new data. Write to the SPI data register only when the SPTE bit is high.
Figure 15-12 shows the timing associated with doing back-to-back transmissions
with the SPI (SPSCK has CPHA–CPOL = 1–0).
Data Sheet
228
Serial Peripheral Interface (SPI)
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MC68HC08AS32A — Rev. 1
MOTOROLA