MC68HC08AS32A Datasheet, PDF (205/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 14-8. POR Recovery
14.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in
the SIM reset status register (SRSR) if the COPD bit in the MORA register is at
logic 0. (See Section 6. Computer Operating Properly (COP).)
14.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal
instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a
reset.
NOTE: A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode (stop
instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the MORA register is logic 0, the SIM treats the
STOP instruction as an illegal opcode and causes an illegal opcode reset.
14.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset.
The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit
in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset.
14.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when the V_DD
voltage falls to the V_TRIPF voltage. The LVI bit in the SIM reset status register
(SRSR) is set and a chip reset is asserted if the LVIPWR and LVIRST bits in the
MC68HC08AS32A — Rev. 1
MOTOROLA
System Integration Module (SIM)
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Data Sheet
205