MC68HC08AS32A Datasheet, PDF (65/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
Functional Description
NOTE:
Use of the BDLC module in message networking fully implements the SAE
Standard J1850 Class B Data Communication Network Interface specification.
It is recommended that the reader be familiar with the SAE J1850 document and
ISO Serial Communication document prior to proceeding with this section of the
MC68HC08AS32A specification.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-2. BDLC Block Diagram
Addr.
$003B
$003C
$003D
$003E
$003F
Register Name
Bit 7
6
5
4
3
BDLC Analog and Roundtrip ^Read: _ATE
RXPOL
0
Delay Register (BARD) Write:
R
See page 84. _{Reset: 1}
1
0
0
BO3
R
0
0
BDLC Control Register 1 ^Read: _IMSG
CLKS
R1
R0
0
(BCR1) Write:
R
See page 86. _{Reset: 1}
1
1
0
0
BDLC Control Register 2 ^Read:
(BCR2) Write:
See page 88. _Reset:
ALOOP
1
DLOOP
1
RX4XE
0
NBFS
0
TEOD
0
BDLC State Vector Register ^{Read: 0}
0
I3
I2
I1
(BSVR) Write: R
R
R
R
R
See page 93. _{Reset: 0}
0
0
0
0
BDLC Data Register ^Read: _BD7
BD6
BD5
BD4
BD3
(BDR) Write:
See page 95. _Reset:
Unaffected by reset
R = Reserved
Figure 4-3. BDLC I/O Register Summary
2
1
Bit 0
BO2
BO1
BO0
1
1
1
0
IE
WCM
R
0
0
0
TSIFR TMIFR1 TMIFR0
0
0
0
I0
0
0
R
R
R
0
0
0
BD2
BD1
BD0
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
65