MC68HC08AS32A Datasheet, PDF (77/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Idle Bus
In Figure 4-10(2), if the passive-to-active received transition beginning the
start-of-frame (SOF) symbol of the next message does not occur before d, the
bus is considered to be idle, and any node wishing to transmit a message may
do so immediately.
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
PASSIVE
a
b
ACTIVE
(3) VALID ACTIVE LOGIC 0
PASSIVE
ACTIVE
b
c
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 4-11. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 4-11(1), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between the passive-to-active transition beginning
the current data bit (or symbol) and a, the current bit would be invalid.
Valid Active Logic 1
In Figure 4-11(2), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between a and b, the current bit would be considered
a logic 1.
Valid Active Logic 0
In Figure 4-11(3), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between b and c, the current bit would be considered
a logic 0.
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
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Data Sheet
77