MC68HC08AS32A Datasheet, PDF (243/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
Functional Description
Addr.
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
Register Name
Timer Channel 2 Register High ^Read:
(TCH2H) Write:
See page 260. _Reset:
Timer Channel 2 Register Low ^Read:
(TCH2L) Write:
See page 260. _Reset:
Timer Channel 3 Status and ^Read:
Control Register (TSC3) Write:
See page 256. _Reset:
Timer Channel 3 Register High ^Read:
(TCH3H) Write:
See page 260. _Reset:
Timer Channel 3 Register Low ^Read:
(TCH3L Write:
See page 260.) _Reset:
Timer Channel 4 Status and ^Read:
Control Register (TSC4) Write:
See page 256. _Reset:
Timer Channel 4 Register High ^Read:
(TCH4H) Write:
See page 260. _Reset:
Timer Channel 4 Register Low ^Read:
(TCH4L) Write:
See page 260. _Reset:
Timer Channel 5 Status and ^Read:
Control Register (TSC5) Write:
See page 256. _Reset:
Timer Channel 5 Register High ^Read:
(TCH5H) Write:
See page 260. _Reset:
Timer Channel 5 Register Low ^Read:
(TCH5L) Write:
See page 260. _Reset:
Bit 7
Bit 15
Bit 7
CH3F
0
0
Bit 15
Bit 7
CH4F
0
0
Bit 15
Bit 7
CH5F
0
0
Bit 15
Bit 7
6
5
4
3
2
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
CH3IE
Indeterminate after reset
0
MS3A ELS3B ELS3A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
Indeterminate after reset
CH4IE MS4B MS4A ELS4B ELS4A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
CH5IE
Indeterminate after reset
0
MS5A ELS5B ELS5A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
= Unimplemented
Indeterminate after reset
Figure 16-3. TIM I/O Register Summary (Continued)
1
Bit 0
9
Bit 8
1
Bit 0
TOV3 CH3MAX
0
0
9
Bit 8
1
Bit 0
TOV4 CH4MAX
0
0
9
Bit 8
1
Bit 0
TOV5 CH5MAX
0
0
9
Bit 8
1
Bit 0
MC68HC08AS32A — Rev. 1
MOTOROLA
Timer Interface (TIM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
243