MC68HC08AS32A Datasheet, PDF (210/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
14.5.2 Reset
All reset sources always have higher priority than interrupts and cannot be
arbitrated.
14.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable
break point by asserting its break interrupt output. (See 17.2 Break Module
(BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector
location. Refer to the break interrupt subsection of each module to see how the
break state affects each module.
14.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared
during break mode. The user can select to protect flags from being cleared by
properly initializing the break clear flag enable bit (BCFE) in the SIM break flag
control register (SBFCR). (See 14.7.3 SIM Break Flag Control Register.)
Protecting flags in break mode ensures that set flags will not be cleared while in
break mode. This protection allows registers to be freely read and written during
break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break
mode, a flag remains cleared even when break mode is exited. Status flags with a
2-step clearing mechanism — for example, a read of one register followed by the
read or write of another — are protected, even when the first step is accomplished
prior to entering break mode. Upon leaving break mode, execution of the second
step will clear the flag as usual.
14.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power mode for
standby situations. The SIM holds the CPU in a non-clocked state. The operation
of each of these modes is described below. Both STOP and WAIT clear the
interrupt mask (I) in the condition code register, allowing interrupts to occur.
14.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks
continues to run. Figure 14-13 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if
the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT
instruction during which the interrupt occurred. Refer to the wait mode subsection
of each module to see if the module is active or inactive in wait mode. Some
modules can be programmed to be active in wait mode.
Data Sheet
210
System Integration Module (SIM)
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MC68HC08AS32A — Rev. 1
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