MC68HC08AS32A Datasheet, PDF (199/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Data Sheet — MC68HC08AS32A
Section 14. System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM), which supports up to
24 external and/or internal interrupts. The SIM is a system state controller that
coordinates CPU and exception timing. Together with the central processor unit
(CPU), the SIM controls all MCU activities.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer
operating properly (COP) timeout
• Interrupt control
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
A block diagram of the SIM is shown in Figure 14-2.
Figure 14-3 is a summary of the SIM input/output (I/O) registers.
Table 14-1 shows the internal signal names used in this section.
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Table 14-1. Signal Name Conventions
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC08AS32A — Rev. 1
MOTOROLA
System Integration Module (SIM)
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Data Sheet
199