MC68HC08AS32A Datasheet, PDF (151/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
PIT During Break Interrupts
11.5.2 Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP instruction
does not affect register conditions or the state of the PIT counter. PIT operation
resumes when the MCU exits stop mode after an external interrupt.
11.6 PIT During Break Interrupts
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state (see
Figure 14-20. SIM Break Flag Control Register (SBFCR)).
To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write I/O registers during
the break state without affecting status bits. Some status bits have a 2-step
read/write clearing procedure. If software does the first step on such a bit before
the break, the bit cannot change during the break state as long as BCFE is at
logic 0. After the break, doing the second step clears the status bit.
11.7 I/O Registers
The following I/O registers control and monitor operation of the PIT:
• PIT status and control register (PSC)
• PIT counter registers (PCNTH–PCNTL)
• PIT counter modulo registers (PMODH–PMODL)
11.7.1 PIT Status and Control Register
The PIT status and control register:
• Enables PIT interrupt
• Flags PIT overflows
• Stops the PIT counter
• Resets the PIT counter
• Prescales the PIT counter clock
MC68HC08AS32A — Rev. 1
MOTOROLA
Programmable Interrupt Timer (PIT)
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Data Sheet
151