MC68HC08AS32A Datasheet, PDF (113/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
The discrepancy in these definitions makes it difficult to specify an acquisition or
lock time for a typical PLL. Therefore, the definitions for acquisition and lock times
for this module are:
• Acquisition time, t_ACQ, is the time the PLL takes to reduce the error between
the actual output frequency and the desired output frequency to less than
the tracking mode entry tolerance, ∆_TRK. Acquisition time is based on an
initial frequency error, [(f_DES – f_ORIG)/f_DES], of not more than ±100%. In
automatic bandwidth control mode (see 5.3.2.3 Automatic and Manual
PLL Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
• Lock time, t_Lock, is the time the PLL takes to reduce the error between the
actual output frequency and the desired output frequency to less than the
lock mode entry tolerance, ∆_Lock. Lock time is based on an initial frequency
error, [(f_DES – f_ORIG)/f_DES], of not more than ±100%. In automatic
bandwidth control mode, lock time expires when the LOCK bit becomes set
in the PLL bandwidth control register (PBWC). (See 5.3.2.3 Automatic and
Manual PLL Bandwidth Modes.)
Obviously, the acquisition and lock times can vary according to how large the
frequency error is and may be shorter or longer in many cases.
5.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still
providing the highest possible stability. These reaction times are not constant,
however. Many factors directly and indirectly affect the acquisition time.
The most critical parameter which affects the PLL reaction times is the reference
frequency, f_RDV. This frequency is the input to the phase detector and controls how
often the PLL makes corrections. For stability, the corrections must be small
compared to the desired frequency, so several corrections are required to reduce
the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is also under user control via the choice of an
external crystal frequency, f_XCLK.
Another critical parameter is the external filter capacitor. The PLL modifies the
voltage on the VCO by adding or subtracting charge from this capacitor. Therefore,
the rate at which the voltage changes for a given frequency error (thus change in
charge) is proportional to the capacitor size. The size of the capacitor also is related
to the stability of the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the capacitor is
too large, the PLL may not be able to adjust the voltage in a reasonable time. (See
5.9.3 Choosing a Filter Capacitor.)
Also important is the operating voltage potential applied to the PLL analog portion
potential (V_DDA/V_DDAREF). Typically, V_DDA/V_DDAREF is at the same potential as
V_DD. The power supply potential alters the characteristics of the PLL. A fixed value
MC68HC08AS32A — Rev. 1
MOTOROLA
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
113