MC68HC08AS32A Datasheet, PDF (74/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Data Sheet
74
ACTIVE
PASSIVE
ACTIVE
PASSIVE
128 µs
OR
(A) LOGIC 0
128 µs
OR
(B) LOGIC 1
64 µs
64 µs
≥ 240 µs
200 µs
200 µs
(C) BREAK
280 µs
(D) START OF FRAME
300 µs
20 µs
(E) END OF DATA
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 4-8. J1850 VPW Symbols with Nominal Symbol Times
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active
period 200 µs in length (see Figure 4-8(d)). This allows the data bytes which
follow the SOF symbol to begin with a passive bit, regardless of whether it is a
logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a
passive period 200 µs in length (see Figure 4-8(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a
passive period 280 µs in length (see Figure 4-8(f)). If no IFR byte is transmitted
after an EOD symbol is transmitted, after another 80 µs the EOD becomes an
EOF, indicating completion of the message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS
symbol contains no transition, since when used it always appends to an EOF
symbol (see Figure 4-8(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
Byte Data Link Controller-Digital (BDLC-D)
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MC68HC08AS32A — Rev. 1
MOTOROLA