MC68HC08AS32A Datasheet, PDF (107/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
5.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
5.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) (See 5.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) (See 5.5.2 PLL Bandwidth
Control Register.)
• PLL programming register (PPG) (See 5.5.3 PLL Programming Register.)
Figure 5-2 is a summary of the CGM registers.
5.5.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the on/off
switch, and the base clock selector bit.
Address:
Read:
Write:
Reset:
$001C
Bit 7
PLLIE
0
6
5
PLLF
PLLON
0
1
= Unimplemented
4
3
2
1
1
BCS
R
R
0
1
1
R
= Reserved
1
Bit 0
1
1
R
R
1
1
Figure 5-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the
LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL
bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads
as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an
interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when
the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the
PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on
the PLL control register clears the PLLF bit.
MC68HC08AS32A — Rev. 1
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
107