MC68HC08AS32A Datasheet, PDF (252/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
16.7.1 TIM Clock Pin (PTD6/ATD14/TCLK)
PTD6/ATD14/TCLK is an external clock input that can be the clock source for the
TIM counter instead of the prescaled internal bus clock. Select the
PTD6/ATD14/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2–0]. (See 16.8.1 TIM Status and Control Register.) The minimum TCLK
pulse width is specified in 18.12 Timer Module Characteristics. The maximum
TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC channel
when not used as the TIM clock input. When the PTD6/ATD14/TCLK pin is the TIM
clock input, it is an input regardless of the state of the DDRD6 bit in data direction
register D.
16.7.2 TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and PTE3/TCH1–PTE2/TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an
output compare pin. PTE2/TCH0, PTE6/TCH2, and PTF2/TCH4 can be configured
as buffered output compare or buffered PWM pins.
16.8 I/O Registers
These I/O registers control and monitor TIM operation:
• TIM status and control register (TSC)
• TIM control registers (TCNTH–TCNTL)
• TIM counter modulo registers (TMODH–TMODL)
• TIM channel status and control registers (TSC0, TSC1, TSC2, TSC3, TSC4,
and TSC5)
• TIM channel registers (TCH0H–TCH0L, TCH1H–TCH1L, TCH2H–TCH2L,
TCH3H–TCH3L, TCH4H–TCH4L, and TCH5H–TCH5L)
16.8.1 TIM Status and Control Register
The TIM status and control register:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Data Sheet
252
Timer Interface (TIM)
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MC68HC08AS32A — Rev. 1
MOTOROLA