MC68HC08AS32A Datasheet, PDF (234/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
15.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR, $0010)
• SPI status and control register (SPSCR, $0011)
• SPI data register (SPDR, $0012)
15.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
Read:
SPRIE
Write:
R
SPMSTR CPOL CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
= Unimplemented
Figure 15-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit.
The SPRF bit is set when a byte transfers from the shift register to the receive
data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between
transmissions. (See Figure 15-5 and Figure 15-7.) To transmit data between
SPI modules, the SPI modules must have identical CPOL bits. Reset clears the
CPOL bit.
Data Sheet
234
Serial Peripheral Interface (SPI)
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MC68HC08AS32A — Rev. 1
MOTOROLA