MC68HC08AS32A Datasheet, PDF (211/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Low-Power Modes
Wait mode also can be exited by a reset (or break in emulation mode). A break
interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask option
register (MORA $001F) is logic 0, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 14-13. Wait Mode Entry Timing
Figure 14-14 and Figure 14-15 show the timing for wait recovery.
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 14-14. Wait Recovery from Interrupt
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 14-15. Wait Recovery from Internal Reset
MC68HC08AS32A — Rev. 1
MOTOROLA
System Integration Module (SIM)
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Data Sheet
211