MC68HC08AS32A Datasheet, PDF (84/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
4.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and
consists of five user registers.
• BDLC analog and roundtrip delay register (BARD)
• BDLC control register 1 (BCR1)
• BDLC control register 2 (BCR2)
• BDLC state vector register (BSVR)
• BDLC data register (BDR)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-16. BDLC Block Diagram
4.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different
external transceivers. The default delay value is16 µs. Timing adjustments from
9 µs to 24 µs in steps of 1 µs are available. The BARD register can be written only
once after each reset, after which they become read-only bits. The register may be
read at any time.
Address: $003B
Bit 7
6
5
Read:
0
ATE
RXPOL
Write:
R
Reset: 1
1
0
R = Reserved
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
R
0
0
1
1
1
Figure 4-17. BDLC Analog and Roundtrip Delay Register (BARD)
Data Sheet
84
Byte Data Link Controller-Digital (BDLC-D)
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MC68HC08AS32A — Rev. 1
MOTOROLA