MC68HC08AS32A Datasheet, PDF (255/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
I/O Registers
16.8.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter.
When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes
set, and the TIM counter resumes counting from $0000 at the next timer clock.
Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until
the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Register Name and Address
TMODH — $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 1
1
1
1
1
1
1
1
NOTE:
Register Name and Address
TMODL — $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 16-7. TIM Counter Modulo Registers (TMODH and TMODL)
Reset the TIM counter before writing to the TIM counter modulo registers.
16.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture
trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
MC68HC08AS32A — Rev. 1
MOTOROLA
Timer Interface (TIM)
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Data Sheet
255