MC68HC08AS32A Datasheet, PDF (73/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after expiration of
the IFS period (for instance, ≥ 300 µs). Any node sensing an idle bus condition
can begin transmission immediately.
4.4.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding technique in
which each bit is defined by the time between successive transitions and by the
level of the bus between transitions (for instance, active or passive). Active and
passive bits are used alternately. This encoding technique is used to reduce the
number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active
or passive level and one of two lengths, either 64 µs or 128 µs (t_NOM at 10.4 kbps
baud rate), depending upon the encoding of the previous bit. The start-of-frame
(SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame separation (IFS)
symbols always will be encoded at an assigned level and length. See Figure 4-8.
Each message will begin with an SOF symbol an active symbol and, therefore,
each data byte (including the CRC byte) will begin with a passive bit, regardless of
whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4
kbps bit rate.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period 64 µs in
length, or
– A passive-to-active transition followed by an active period 128 µs in
length
See Figure 4-8(a).
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period 128 µs in
length, or
– A passive-to-active transition followed by an active period 64 µs in
length
See Figure 4-8(b).
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is only used
in IFR message responses.
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an
active period of at least 240 µs (see Figure 4-8(c)).
MC68HC08AS32A — Rev. 1
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
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Data Sheet
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