MC68HC08AS32A Datasheet, PDF (45/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Memory
Electrically Erasable Programmable ROM (EEPROM)
E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will
only clear EEPGM. This is to allow time for the completion of the on-board
programming sequence and the removal of high voltage from the EEPROM array.
F. It is proper to disable interrupts prior to performing a program cycle. If the cycle
is interrupted, the data that is programmed could be corrupt.
2.5.1.8 EEPROM Erasing
The programmed state of an EEPROM bit is logic 0. Erasing changes the state to
a logic 1. Only EEPROM bytes in the non-protected blocks and the EENVR register
can be erased.
NOTE:
Using the following procedure to erase a byte, block or the entire EEPROM array:
1. Configure EERAS1 and EERAS0 for byte, block, or bulk erase; set EELAT
in EECR.^(A)
If using the AUTO mode, also set the AUTO bit in Step 1.
2. Byte erase: write any data to the desired address.^(B)
Block erase: write any data to an address within the desired block.^(B)
Bulk erase: write any data to an address within the array.^(B)
3. Set the EEPGM bit.^(C) Go to Step 6 if AUTO is set.
4. Wait for a time, t_EEBYTE for byte erase; t_EEBLOCK for block erase; t_EEBULK for
bulk erase.
5. Clear EEPGM bit. Go to Step 7.
6. Poll the EEPGM bit until it is cleared by the state machine.^(D)
7. Wait for a time, t_EEFPV, for the erasing voltage to fall. Go to Step 8.
8. Clear EELAT bits.^(E)
NOTE:
A. Setting the EELAT bit configures the address and data buses to latch data for
erasing the array. Only valid EEPROM addresses will be latched. If EELAT is set,
other writes to the EECR will be allowed after a valid EEPROM write.
B. If more than one valid EEPROM write occurs, the last address and data will be
latched overriding the previous address and data. Once data is written to the
desired address, do not read EEPROM locations other than the written location.
(Reading an EEPROM location returns the latched data and causes the read
address to be latched.)
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-valid
EEPROM address is latched. This is to ensure proper programming sequence.
Once EEPGM is set, do not read any EEPROM locations; otherwise, the current
program cycle will be unsuccessful. When EEPGM is set, the on-board
programming sequence will be activated. Data cannot be read from the array until
the programming sequence is completed.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than
t_EEBYTE/t_EEBLOCK/t_EEBULK. However, on other MCUs this delay time may be
MC68HC08AS32A — Rev. 1
MOTOROLA
Memory
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
45