MC68HC08AS32A Datasheet, PDF (276/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
V_DD
4096 + 32 CGMXCLK CYCLES
RST
FROM HOST
PA0
4
FROM MCU
1
3
1
1
2
3
1
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
3 = Wait 1 bit time before sending next byte
4 = Wait until clock is stable and monitor runs
Figure 17-13. Monitor Mode Entry Timing
17.3.3 Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is
transferred between the monitor and host at 4800 baud. If the PTC3 pin is at logic 0
during reset, the monitor baud rate is 9600. When the CGM output, CGMOUT, is
driven by the PLL, the baud rate is determined by the MUL[7:4] bits in the PLL
programming register (PPG). See Section 5. Clock Generator Module (CGM).
Table 17-9. Monitor Baud Rate Selection
Monitor Baud Rate (4.9152 MHz)
Monitor Baud Rate (4.194 MHz)
1
4800
4096
VCO Frequency Multiplier (N)
2
3
4
5
9600
14,400
19,200
24,000
8192
12,288
16,384
20,480
6
28,800
24,576
Data Sheet
276
Development Support
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MC68HC08AS32A — Rev. 1
MOTOROLA