MC68HC08AS32A Datasheet, PDF (196/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
13.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the SCI data
register.
NOTE:
Address: $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read: R7
R6
R5
R4
R3
R2
R1
R0
Write: T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 13-16. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing
to the SCDR writes the data to be transmitted, T7:T0. Reset has no effect on the
SCDR.
Do not use read/modify/write instructions on the SCI data register.
13.8.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the
transmitter.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 13-17. SCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in
Table 13-6. Reset clears SCP1 and SCP0.
Table 13-6. SCI Baud Rate Prescaling
SCP1 and SCP0
00
01
10
11
Prescaler Divisor (PD)
1
3
4
13
Data Sheet
196
Serial Communications Interface (SCI)
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Go to: www.freescale.com
MC68HC08AS32A — Rev. 1
MOTOROLA