MC68HC08AS32A Datasheet, PDF (250/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare can also cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM
operation. The TIM channel 0 registers (TCH0H–TCH0L) initially control the
buffered PWM output. TIM status control register 0 (TSC0) controls and monitors
the PWM signal from the linked channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM
operation. The TIM channel 2 registers (TCH2H–TCH2L) initially control the
buffered PWM output. TIM status control register 2 (TSC2) controls and monitors
the PWM signal from the linked channels. MS2B takes priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM
operation. The TIM channel 4 registers (TCH4H–TCH4L) initially control the
buffered PWM output. TIM status control register 4 (TSC4) controls and monitors
the PWM signal from the linked channels. MS4B takes priority over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
Subsequent output compares try to force the output to a state it is already in and
have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit
generates a 100% duty cycle output. See 16.8.4 TIM Channel Status and Control
Registers.
16.4 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches
the modulo value programmed in the TIM counter modulo registers. The TIM
overflow interrupt enable bit, TOIE, enables TIM overflow interrupt requests.
TOF and TOIE are in the TIM status and control register.
• TIM channel flags (CH5F–CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. Channel x TIM CPU
interrupt requests are controlled by the channel x interrupt enable bit,
CHxIE.
Data Sheet
250
Timer Interface (TIM)
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MC68HC08AS32A — Rev. 1
MOTOROLA