MC68HC08AS32A Datasheet, PDF (180/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
13.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the
PTE1/RxD pin. The SCI data register (SCDR) is the read-only buffer between the
internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of
the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status
register 1 (SCS1) becomes set, indicating that the received byte can be read. If the
SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit
generates a receiver CPU interrupt request.
13.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an
internal signal with a frequency 16 times the baud rate. To adjust for baud rate
mismatch, the RT clock is resynchronized at the following times (see Figure 13-7):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the
majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1
and the majority of the next RT8, RT9, and RT10 samples returns a valid
logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a
logic 0 preceded by three logic 1s. When the falling edge of a possible start bit
occurs, the RT clock begins to count to 16.
PTE1/RxD
START BIT
LSB
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
Figure 13-7. Receiver Data Sampling
Data Sheet
180
Serial Communications Interface (SCI)
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MC68HC08AS32A — Rev. 1
MOTOROLA