MC68HC08AS32A Datasheet, PDF (212/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
14.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An
interrupt request from a module can cause an exit from stop mode. Stacking for
interrupts begins after the selected stop recovery time has elapsed. Reset or break
also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK)
in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable
using the short stop recovery (SSREC) bit in the MORA register ($001F). If SSREC
is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles
down to 32. This is ideal for applications using canned oscillators that do not
require long startup times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by clearing the
SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the
SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP instruction
until the beginning of stop recovery. It is then used to time the recovery period.
Figure 14-16 shows stop mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 14-16. Stop Mode Entry Timing
CGMXCLK
INTERRUPT
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 14-17. Stop Mode Recovery from Interrupt
Data Sheet
212
System Integration Module (SIM)
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MC68HC08AS32A — Rev. 1
MOTOROLA