MC68HC08AS32A Datasheet, PDF (213/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Registers
14.7 SIM Registers
The SIM has three memory mapped registers.
14.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an
exit from wait mode. This register is only used in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
R
R
R
R
R
SBSW
R
Write:
Reset:
0
R
= Reserved
Figure 14-18. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it.
1 = Wait mode exited by break interrupt
0 = Wait mode not exited by break interrupt
14.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset. The status
register will clear automatically after reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
Address: $FE01
Bit 7
6
5
4
3
2
Read: POR
PIN
COP
ILOP
ILAD
0
Write:
1
Bit 0
LVI
0
Reset: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 14-19. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
MC68HC08AS32A — Rev. 1
MOTOROLA
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
213