MC68HC08AS32A Datasheet, PDF (194/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD
pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is
also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset
clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE
generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set.
Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset
clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in
incoming data. PE generates an SCI error CPU interrupt request if the PEIE bit
in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then
reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
BYTE 1
Data Sheet
194
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 13-14. Flag Clearing Sequence
BYTE 4
Serial Communications Interface (SCI)
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MC68HC08AS32A — Rev. 1
MOTOROLA