MC68HC08AS32A Datasheet, PDF (254/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface (TIM)
PS[2–0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TCLK pin or one of the
seven prescaler outputs as the input to the TIM counter as Table 16-1 shows.
Reset clears the PS[2–0] bits.
Table 16-1. Prescaler Selection
PS[2–0]
000
001
010
011
100
101
110
111
TIM Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTD6/ATD14/TCLK
16.8.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value
in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low
byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched
TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting
the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE:
If TCNTH is read during a break interrupt, be sure to unlatch TCNTL by reading
TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value
latched during the break.
Register Name and Address
TCNTH — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Register Name and Address
TCNTL — $0023
Bit 7 6
5
4
3
2
1
Bit 0
Read: BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. TIM Counter Registers (TCNTH and TCNTL)
Data Sheet
254
Timer Interface (TIM)
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MC68HC08AS32A — Rev. 1
MOTOROLA