MC68HC08AS32A Datasheet, PDF (225/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Error Conditions
15.6 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register before
the next byte enters the shift register sets the OVRF bit. The new byte does
not transfer to the receive data register, and the unread byte still can be read
by accessing the SPI data register. OVRF is in the SPI status and control
register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode of the SPI.
MODF is in the SPI status and control register.
15.6.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register
still has unread data from a previous transmission when the capture strobe of bit 1
of the next transmission occurs. (See Figure 15-5 and Figure 15-7.) If an overflow
occurs, the data being received is not transferred to the receive data register so
that the unread data can still be read. Therefore, an overflow error always indicates
the loss of data.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE in SPSCR) is also set. MODF and OVRF can generate a receiver/error
CPU interrupt request. (See Figure 15-11.) It is not possible to enable only MODF
or OVRF to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait,
having an overflow condition without overflow interrupts enabled causes the MCU
to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull
the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. Figure 15-9 shows how it is possible to miss an overflow.
The first part of Figure 15-9 shows how to read the SPSCR and SPDR to clear the
SPRF without problems. However, as illustrated by the second transmission
example, the OVRF flag can be set in between the time that SPSCR and SPDR are
read.
In this case, an overflow can be easily missed. Since no more SPRF interrupts can
be generated until this OVRF is serviced, it will not be obvious that bytes are being
lost as more transmissions are completed. To prevent this, either enable the OVRF
interrupt or do another read of the SPSCR after the read of the SPDR. This ensures
that the OVRF was not set before the SPRF was cleared and that future
transmissions will complete with an SPRF interrupt. Figure 15-10 illustrates this
process. Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
MC68HC08AS32A — Rev. 1
MOTOROLA
Serial Peripheral Interface (SPI)
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Data Sheet
225