MC68HC08AS32A Datasheet, PDF (157/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
Port A
12.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an
output. Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
NOTE:
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
Figure 12-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0],
configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Avoid glitches on port A pins by writing to the port A data register before changing
data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch.
When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 12-1 summarizes the operation of the port A pins.
MC68HC08AS32A — Rev. 1
MOTOROLA
Input/Output (I/O) Ports
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Data Sheet
157