MC68HC08AS32A Datasheet, PDF (115/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
The K factor in the equations is derived from internal PLL parameters. K_ACQ is the
K factor when the PLL is configured in acquisition mode, and K_TRK is the K factor
when the PLL is configured in tracking mode. (See 5.3.2.2 Acquisition and
Tracking Modes.)
t_ACQ
=


V--f--_{R-D--D-D---V-A-}


-K----_A-8--_C---_Q--_
t_AL
=


V--f--_{R-D--D-D---V-A-}


-K----_T-4--_R---_K--_
t_Lock = t_ACQ + t_AL
NOTE:
There is an inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized
into units based on the reference frequency. (See 5.3.2.3 Automatic and Manual
PLL Bandwidth Modes.) A certain number of clock cycles, n_ACQ, is required to
ascertain that the PLL is within the tracking mode entry tolerance, ∆_TRK, before
exiting acquisition mode. Additionally, a certain number of clock cycles, n_TRK, is
required to ascertain that the PLL is within the lock mode entry tolerance, ∆_Lock.
Therefore, the acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV, and the
acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV. Refer to 5.3.2
Phase-Locked Loop Circuit (PLL) for the value of f_RDV. Also, since the average
frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than t_Lock
before selecting the PLL clock (see 5.3.3 Base Clock Selector Circuit), because
the factors described in 5.9.2 Parametric Influences on Reaction Time can slow
the lock time considerably.
MC68HC08AS32A — Rev. 1
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
115