MC68HC08AS32A Datasheet, PDF (120/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
6.6 Monitor Mode
The COP is disabled in monitor mode when V_TST (see 18.5 5.0-Volt DC Electrical
Characteristics) is present on the IRQ pin or on the RST pin.
6.7 Low-Power Modes
The following subsections describe the low-power modes.
6.7.1 Wait Mode
NOTE:
The COP continues to operate during wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
If the COP is enabled in wait mode, it must be periodically refreshed. (See 6.3.6
COPD (COP Disable).)
6.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter.
Service the COP immediately before entering or after exiting stop mode to ensure
a full COP timeout period after entering or exiting stop mode.
The STOP bit in the MORA register ($001F) (see Section 10. Mask Options)
enables the STOP instruction. To prevent inadvertently turning off the COP with a
STOP instruction, disable the STOP instruction by programming the STOP bit to
logic 0.
6.8 COP Module During Break Interrupts
The COP is disabled during a break interrupt when V_TST (see 18.5 5.0-Volt DC
Electrical Characteristics) is present on the RST pin.
Data Sheet
120
Computer Operating Properly (COP)
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MC68HC08AS32A — Rev. 1
MOTOROLA