MC68HC08AS32A Datasheet, PDF (34/296 Pages) Motorola, Inc – Microcontrollers

Memory
Freescale Semiconductor, Inc.
Addr.
Register Name
Bit 7
6
$001D
PLL Bandwidth Control Register
(PBWC)
See page 108.
Read:
Write:
Reset:
AUTO
LOCK
$001E
PLL Programming Register ^Read:
(PPG) Write:
See page 110. _Reset:
MUL7
0
MUL6
0
$001F
Mask Option Register ^{Read: LVISTOP}
(MORA) Write:
See page 146. _Reset:
ROMSEC
$0020
Timer Status and Control ^{Read: TOF}
TOIE
Register (TSC) Write: 0
See page 253. _{Reset: 0}
0
$0021
Reserved
R
R
5
ACQ
MUL5
0
LVIRST
TSTOP
1
R
4
3
0
XLD
R
MUL4 VRS7
0
0
LVIPWR SSREC
Unaffected by reset
0
0
TRST
0
0
R
R
2
0
R
VRS6
0
COPS
PS2
0
R
1
0
R
VRS5
0
STOP
PS1
0
R
Bit 0
0
R
VRS4
0
COPD
PS0
0
R
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Timer Counter Register High ^Read:
(TCNTH) Write:
See page 254. _Reset:
Timer Counter Register Low ^Read:
(TCNTL) Write:
See page 254. _Reset:
Timer Modulo Register High ^Read:
(TMODH) Write:
See page 255. _Reset:
Timer Modulo Register Low ^Read:
(TMODL) Write:
See page 255. _Reset:
Timer Channel 0 Status and ^Read:
Control Register (TSC0) Write:
See page 256. _Reset:
Timer Channel 0 Register High ^Read:
(TCH0H) Write:
See page 260. _Reset:
Timer Channel 0 Register Low ^Read:
(TCH0L) Write:
See page 260. _Reset:
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
Indeterminate after reset
6
5
4
3
2
1
Bit 0
= Unimplemented
Indeterminate after reset
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Register (Sheet 4 of 8)
Data Sheet
34
Memory
For More Information On This Product,
Go to: www.freescale.com
MC68HC08AS32A — Rev. 1
MOTOROLA