MC68HC08AS32A Datasheet, PDF (146/296 Pages) Motorola, Inc – Microcontrollers

Mask Options
Freescale Semiconductor, Inc.
10.3 Mask Option Registers (MORA and MORB)
Address:
Read:
Write:
Reset:
$001F
Bit 7
LVISTOP
6
ROMSEC
5
LVIRST
4
LVIPWR
3
SSREC
2
COPS
= Unimplemented
Unaffected by reset
Figure 10-1. Mask Option Register (MORA)
1
STOP
Bit 0
COPD
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode.(See Section 9. Low-Voltage
Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
ROMSEC — ROM Security Bit
ROMSEC enables the ROM security feature. Setting the ROMSEC bit prevents
reading of the ROM contents. Access to the ROM is denied to unauthorized
users of customer-specified software.
1 = ROM security enabled
0 = ROM security disabled
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See Section 9.
Low-Voltage Inhibit (LVI).)
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Section 9. Low-Voltage Inhibit (LVI).)
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles
instead of a 4096-CGMXCLK cycle delay. (See 16.5.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPS — COP Rate Select Timeout Bit
COPS selects the short COP timeout period. (See Section 6. Computer
Operating Properly (COP).)
1 = COP timeout period is 2¹³â€“2⁴ CGMXCLK cycles.
0 = COP timeout period is 2¹⁸–2⁴ CGMXCLK cycles.
Data Sheet
146
Mask Options
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MC68HC08AS32A — Rev. 1
MOTOROLA