MC68HC08AS32A Datasheet, PDF (80/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-14. BDLC Block Diagram
4.5.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow
register, Rx shift register, Tx shift register, and loopback multiplexer as shown in
Figure 4-15.
4.5.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and
makes them available in parallel form to the Rx shadow register. The Tx shift
register takes data, in parallel form, from the Tx shadow register and presents it
serially to the state machine so that it can be transmitted onto the J1850 bus.
4.5.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data,
this data is transferred to the Rx shadow register and RDRF or RXIFR is set (see
4.6.4 BDLC State Vector Register) and an interrupt is generated if the interrupt
enable bit (IE) in BCR1 is set. After the transfer takes place, this new data byte in
the Rx shadow register is available to the CPU interface, and the Rx shift register
is ready to shift in the next byte of data. Data in the Rx shadow register must be
retrieved by the CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the current byte,
the data byte in the Tx shadow register is loaded into the Tx shift register. After this
transfer takes place, the Tx shadow register is ready to accept new data from the
CPU when TDRE flag in BSVR is set.
Data Sheet
80
Byte Data Link Controller-Digital (BDLC-D)
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MC68HC08AS32A — Rev. 1
MOTOROLA