MC68HC08AS32A Datasheet, PDF (142/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
V_DD
LVIPWRD
FROM MORA
STOP INSTRUCTION
FROM MORA
LVIRSTD
LVISTOP
FROM MORA
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVIOUT
LVI RESET
Figure 9-1. LVI Module Block Diagram
9.4 LVI Status Register
The LVI status register flags V_DD voltages below the V_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_TRIPF
voltage (see Table 9-1). Reset clears the LVIOUT bit.
Table 9-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
Previous value
9.5 LVI Interrupts
The LVI module does not generate interrupt requests.
Data Sheet
142
Low-Voltage Inhibit (LVI)
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MC68HC08AS32A — Rev. 1
MOTOROLA