MC68HC08AS32A Datasheet, PDF (266/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
17.2.2.1 Break Status and Control Register
The break status and control register contains break module enable and status
bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 17-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear
BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs.
Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a
logic 0 to it before exiting the break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
17.2.2.2 Break Address Registers
The break address registers contain the high and low bytes of the desired
breakpoint address. Reset clears the break address registers.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 15 BIT 13 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 17-4. Break Address Register (BRKH)
Address: $FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 17-5. Break Address Register (BRKL)
Data Sheet
266
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MC68HC08AS32A — Rev. 1
MOTOROLA