MC68HC08AS32A Datasheet, PDF (140/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
External Interrupt (IRQ)
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the ACK bit in the IRQ status and control register
during the break state has no effect on the IRQ latch.
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the
IRQ module. The ISCR:
• Shows the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001A
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
IRQF
0
IMASK
Write:
ACK
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 8-5. IRQ Status and Control Register (ISCR)
Bit 0
MODE
0
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears
IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears
MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Data Sheet
140
External Interrupt (IRQ)
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MC68HC08AS32A — Rev. 1
MOTOROLA