MC68HC08AS32A Datasheet, PDF (264/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
IAB[15:8]
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
TO SIM
IAB[7:0]
Figure 17-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
Break Address Register High ^Read: _{Bit 15}
14
13
12
11
10
$FE0C
(BRKH) Write:
See page 266. _Reset:
0
0
0
0
0
0
Break Address Register Low ^Read: _{Bit 7}
6
5
4
3
2
$FE0D
(BRKL) Write:
See page 266.
Reset:
0
0
0
0
0
0
Read:
0
0
0
0
Break Status and Control
BRKE BRKA
$FE0E
Register (BRKSCR) Write:
See page 266. _Reset:
0
0
0
0
0
0
= Unimplemented
Figure 17-2. Break I/O Register Summary
1
Bit 0
9
Bit 8
0
0
1
Bit 0
0
0
0
0
0
0
When the internal address bus matches the value written in the break address
registers or when software writes a logic 1 to the BRKA bit in the break status and
control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD
in monitor mode)
Data Sheet
264
Development Support
For More Information On This Product,
Go to: www.freescale.com
MC68HC08AS32A — Rev. 1
MOTOROLA