MC68HC08AS32A Datasheet, PDF (76/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
Valid Passive Logic 0
See Figure 4-9(2). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between a and b, the current bit would be
considered a logic 0.
Valid Passive Logic 1
See Figure 4-9(3). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between b and c, the current bit would be
considered a logic 1.
Valid EOD Symbol
See Figure 4-9(4). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between c and d, the current symbol would be
considered a valid end-of-data symbol (EOD).
300 µs
280 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 4-10. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbol
In Figure 4-10(1), if the passive-to-active received transition beginning the SOF
symbol of the next message occurs between a and b, the current symbol will be
considered a valid end-of-frame (EOF) symbol.
See Figure 4-10(2). If the passive-to-active received transition beginning the
SOF symbol of the next message occurs between c and d, the current symbol
will be considered a valid EOF symbol followed by a valid inter-frame separation
symbol (IFS). All nodes must wait until a valid IFS symbol time has expired
before beginning transmission. However, due to variations in clock frequencies
and bus loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node waiting to
transmit detects a passive-to-active transition once a valid EOF has been
detected, it should immediately begin transmission, initiating the arbitration
process.
Data Sheet
76
Byte Data Link Controller-Digital (BDLC-D)
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MC68HC08AS32A — Rev. 1
MOTOROLA