MC68HC08AS32A Datasheet, PDF (263/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Data Sheet — MC68HC08AS32A
Section 17. Development Support
17.1 Introduction
This section describes the break module, the monitor read-only memory (MON),
and the monitor mode entry methods.
17.2 Break Module (BRK)
This section describes the break module (break). The break module can generate
a break interrupt that stops normal program flow at a defined address to enter a
background program.
Features of the break module include:
• Accessible I/O registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
17.2.1 Functional Description
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM
then causes the CPU to load the instruction register with a software interrupt
instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches
the contents of the break address registers
• Software writes a logic 1 to the BRKA bit in the break status and control
register.
When a CPU-generated address matches the contents of the break address
registers, the break interrupt is generated. A return-from-interrupt instruction (RTI)
in the break routine ends the break interrupt and returns the MCU to normal
operation. Figure 17-1 shows the structure of the break module. Figure 17-2
provides a summary of the I/O registers.
MC68HC08AS32A — Rev. 1
MOTOROLA
Development Support
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Data Sheet
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