MC68HC08AS32A Datasheet, PDF (207/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Program Exception Control
14.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the
stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end
of an interrupt, the RTI instruction recovers the CPU register contents from the
stack so that normal processing can resume. Figure 14-9 shows interrupt entry
timing. Figure 14-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of
interrupt processing. The arbitration result is a constant that the CPU uses to
determine which vector to fetch. Once an interrupt is latched by the SIM, no other
interrupt can take precedence, regardless of priority, until the latched interrupt is
serviced or the I bit is cleared. (See Figure 14-11.)
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC–1[7:0] PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
Figure 14-9. Hardware Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1 [15:8] PC–1[7:0] OPCODE OPERAND
Figure 14-10. Hardware Interrupt Recovery
MC68HC08AS32A — Rev. 1
MOTOROLA
System Integration Module (SIM)
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Data Sheet
207