MC68HC08AS32A Datasheet, PDF (161/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
Port C
12.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an
output. Writing a logic 1 to a DDRC bit enables the output buffer for the
corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
4
3
2
1
Read:
0
MCLKEN
Write:
0
DDRC4 DDRC3 DDRC2 DDRC1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 12-9. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
NOTE:
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is
enabled, PTC2 is under the control of MCLKEN. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0],
configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
Avoid glitches on port C pins by writing to the port C data register before changing
data direction register C bits from 0 to 1.
Figure 12-10 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
DDRCx
PTCx
PTCx
READ PTC ($0002)
Figure 12-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch.
When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the
MC68HC08AS32A — Rev. 1
MOTOROLA
Input/Output (I/O) Ports
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Data Sheet
161