MC68HC08AS32A Datasheet, PDF (202/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals
on the MCU. The system clocks are generated from an incoming clock, CGMOUT,
as shown in Figure 14-4. This clock can come from either an external oscillator or
from the on-chip PLL. (See Section 5. Clock Generator Module (CGM).)
14.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output
(CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. (See
Section 5. Clock Generator Module (CGM).)
14.2.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI) module
generates a reset, the clocks to the CPU and peripherals are inactive and held in
an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by
the SIM during this entire period. The bus clocks start upon completion of the
timeout.
14.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to
clock the SIM counter. The CPU and peripheral clocks do not become active until
after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK
cycles. (See 14.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can be
programmed to be active in wait mode. Refer to the wait mode subsection of each
module to see if the module is active or inactive in wait mode.
OSC1
Data Sheet
202
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 14-4. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
System Integration Module (SIM)
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MC68HC08AS32A — Rev. 1
MOTOROLA