MC68HC08AS32A Datasheet, PDF (190/296 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
NOTE:
NOTE:
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt
requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt
requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10
or 11 logic 1s from the transmit shift register to the PTE0/TxD pin. If software
clears the TE bit, the transmitter completes any transmission in progress before
the PTE0/TxD returns to the idle condition (logic 1). Clearing and then setting
TE during a transmission queues an idle character to be sent after the character
currently being transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI
is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the
receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver
interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input
or an address mark brings the receiver out of the standby state and clears the
RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed
by a logic 1. The logic 1 after the break character guarantees recognition of a
valid start bit. If SBK remains set, the transmitter continuously transmits break
characters with no logic 1s between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
Data Sheet
190
Serial Communications Interface (SCI)
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MC68HC08AS32A — Rev. 1
MOTOROLA